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dt-code [2024/03/12 00:19] beckmanf add signal |
dt-code [2025/04/10 16:09] (current) beckmanf bilder in dokuwiki |
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| The code in listing 1 describes the full code for a circuit called "and_gate". The entity with the name "and_gate" describes two input ports "a_i" and "b_i" and an output port "y_o". All ports here have the type "std_ulogic" which defines that those ports basically can have a logic 1 or 0 value. (Some other values for simulation purposes are left for now). An entity can have an arbitrary number of inputs and outputs. Each input and output can have a different type. | The code in listing 1 describes the full code for a circuit called "and_gate". The entity with the name "and_gate" describes two input ports "a_i" and "b_i" and an output port "y_o". All ports here have the type "std_ulogic" which defines that those ports basically can have a logic 1 or 0 value. (Some other values for simulation purposes are left for now). An entity can have an arbitrary number of inputs and outputs. Each input and output can have a different type. | ||
| - | <html> | + | {{ :public:praktikum_digitaltechnik:and_gate.svg?width=300 |AND Gate Block}} |
| - | <img src="http://breakout.hs-augsburg.de/dwimg/and_gate.svg" width="300" > | + | |
| - | </html> | + | |
| - | Figure 1: Block and_gate with a_i and b_i as inputs and y_o as output | + | {{ :public:praktikum_digitaltechnik:and_gate.svg?linkonly |Figure 1}}: Block and_gate with a_i and b_i as inputs and y_o as output |
| Figure 1 shows the block "and_gate" with the inputs and outputs. This represents the entity. The entity code does not imply any functionality. The name "and_gate" is an identifier, i.e. it does not imply that this block actually works as an and gate. | Figure 1 shows the block "and_gate" with the inputs and outputs. This represents the entity. The entity code does not imply any functionality. The name "and_gate" is an identifier, i.e. it does not imply that this block actually works as an and gate. | ||
| - | <html> | + | {{ :public:praktikum_digitaltechnik:and_gate_arch.svg?width=300 |}} |
| - | <img src="http://breakout.hs-augsburg.de/dwimg/and_gate_arch.svg" width="300" > | + | |
| - | </html> | + | |
| - | Figure 2: Architecture of "and_gate" which just contains and AND gate. | + | {{ :public:praktikum_digitaltechnik:and_gate_arch.svg?linkonly |Figure 2}}: Architecture of "and_gate" which just contains an AND gate. |
| The architecture with the name "rtl" describes the implementation. Here it is a signal assignment with a boolean expression using the and function. This makes this circuit behave like an AND gate. Figure 2 shows the schematic with the AND gate. As the AND function can be described in one line of code, this block "and_gate" does not make too much sense, but it explains the idea of entity and architecture. | The architecture with the name "rtl" describes the implementation. Here it is a signal assignment with a boolean expression using the and function. This makes this circuit behave like an AND gate. Figure 2 shows the schematic with the AND gate. As the AND function can be described in one line of code, this block "and_gate" does not make too much sense, but it explains the idea of entity and architecture. | ||
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| Circuits are very often composed of subcircuits. And the subcircuits can themself be composed of subcircuits. This is called hierarchical design. The following example shows a block "mux". | Circuits are very often composed of subcircuits. And the subcircuits can themself be composed of subcircuits. This is called hierarchical design. The following example shows a block "mux". | ||
| + | {{ :public:praktikum_digitaltechnik:mux.svg?width=200 | Multipexer block}} | ||
| - | <html> | + | {{ :public:praktikum_digitaltechnik:mux.svg?linkonly |Figure 3}}: "mux" block with a_i, b_i and s_i inputs and y_o output |
| - | <img src="http://breakout.hs-augsburg.de/dwimg/mux.svg" width="200" > | + | |
| - | </html> | + | |
| - | + | ||
| - | Figure 3: "mux" block with a_i, b_i and s_i inputs and y_o output | + | |
| Figure 3 shows the block interface of a circuit "mux" which has three inputs a_i, b_i and s_i and an output y_o. | Figure 3 shows the block interface of a circuit "mux" which has three inputs a_i, b_i and s_i and an output y_o. | ||
| Line 55: | Line 48: | ||
| Assume that we have defined not only the "and_gate" but also an "or_gate" and an "inv_gate". The mux circuit shall be composed of the xxx_gate subcircuits as shown in figure 4. | Assume that we have defined not only the "and_gate" but also an "or_gate" and an "inv_gate". The mux circuit shall be composed of the xxx_gate subcircuits as shown in figure 4. | ||
| - | <html> | + | {{ :public:praktikum_digitaltechnik:mux-vhdl.svg?width=800 | Mux Schematic}} |
| - | <img src="http://breakout.hs-augsburg.de/dwimg/mux-vhdl.svg" width="800" > | + | |
| - | </html> | + | |
| - | Figure 4: Schematic of "mux" | + | {{ :public:praktikum_digitaltechnik:mux-vhdl.svg?linkonly |Figure 4}}: Schematic of "mux" |
| Figure 4 shows a schematic of a multiplexer using and_gate, or_gate and the inv_gate. The corresponding VHDL code is shown in listing 2. | Figure 4 shows a schematic of a multiplexer using and_gate, or_gate and the inv_gate. The corresponding VHDL code is shown in listing 2. | ||