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| msvsli_start [2026/04/21 06:51] – [Introduction and Overview] add openroad flow beckmanf | msvsli_start [2026/06/01 15:44] (current) – [Process Development Kit (PDK)] beckmanf |
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| SiliWizz: [[https://tinytapeout.com/siliwiz/introduction/|https://tinytapeout.com/siliwiz/introduction/]] | SiliWizz: [[https://tinytapeout.com/siliwiz/introduction/|https://tinytapeout.com/siliwiz/introduction/]] |
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| | [[https://link.springer.com/book/10.1007/978-3-030-96415-3|Andrew B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure, Springer, 2022]] |
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| | [[https://www.ifte.de/books/eda/index.html | VLSI Physical Design - Slides , 2022]] |
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| | [[https://safari.ethz.ch/ddca/spring2026/doku.php?id=start | Onur Mutlu, Digital Design and Computer Architecture, ETH Zürich, 2026]] |
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| ==== Introduction and Overview ==== | ==== Introduction and Overview ==== |
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| [[https://raw.githubusercontent.com/fredowski/Course/tha/build/c04_lecture.pdf | Chapter 04 pdf]] | [[https://raw.githubusercontent.com/fredowski/Course/tha/build/c04_lecture.pdf | Chapter 04 pdf]] |
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| | ==== Process Design Kit (PDK) ==== |
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| | [[https://raw.githubusercontent.com/fredowski/Course/tha/build/c05_lecture.pdf | Chapter 05 pdf]] |
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| | ==== Timing Verification / Static Timing Analysis ==== |
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| | {{ ::msvlsi-timing.pdf | Timing Analysis and Pipelining }} |
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| | [[https://www.ifte.de/books/eda/chap8.pdf | Andrew Kahng - Chapter 8 Slides - Timing Closure]] |
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| | ==== Partitioning / KL Algorithm ==== |
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| | [[https://www.ifte.de/books/eda/chap2.pdf | Andrew Kahng - Chapter 2 Slides - Partitioning]] |
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| | ==== Placement ==== |
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| | [[https://www.ifte.de/books/eda/chap4.pdf | Andrew Kahng - Chapter 4 Slides - Placement]] |
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| | OpenROAD uses the RUDY Routing Congestion Estimation based on the following paper: |
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| | [[https://ieeexplore.ieee.org/document/4211973 | P. Spindler, F. M. Johannes, Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement, in Design, Automation and Test in Europe Conference 2007, April 2007. DOI: 10.1109/DATE.2007.364463.]] |
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| | ==== Routing ==== |
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| | [[https://www.ifte.de/books/eda/chap5.pdf | Andrew Kahng - Chapter 5 Slides - Global Routing]] |
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| | [[https://www.ifte.de/books/eda/chap7.pdf | Andrew Kahng - Chapter 7 Slides - Clock Tree Synthesis]] |
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| | ==== Machine Learning in Chip Design ==== |
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| | [[https://github.com/FeSens/auto-arch-tournament/blob/main/docs/auto-arch-tournament-blog-post.md | Felipe Sens Bonetto, Apply autoresearch to a RISC-V CPU design, github 2026 ]] |
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| | [[https://youtu.be/2A3tiAmaq_c?t=1480 | Youtube: Jeff Dean, Jeff Dean: AI will Reshape Chip Design, NeurIPS 2024 ]] |
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| | [[https://arxiv.org/pdf/2302.11014 | Chung-Kuan Cheng, Andrew B. Kahng, et al., "An Updated Assessment of Reinforcement Learning for Macro Placement", arxiv.org, March 2026 ]] |
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