=== Die erste Schaltung ===

besteht aus zwei VHDL Dateien, der eigentlichen Schaltung und 
einer Testbench, mit der die Schaltung simuliert werden kann. 

== Die Schaltung ==

<code vhdl first.vhd>
library ieee;
use ieee.std_logic_1164.all;

-- Simple module that connects the SW switches to the LEDR lights
entity first is 
port ( SW   : in      std_ulogic_vector(9 downto 0);
       LEDR : out     std_ulogic_vector(9 downto 0));  -- red LEDs
end first;

architecture structure of first is
begin
  LEDR <= SW;
end structure;

</code>

== Die Testbench ==

<code vhdl first_tb.vhd>
library ieee;
use ieee.std_logic_1164.all;

-- Testbench for the first switch/led module
-- The switches are switched...

entity first_tb is
end; 

architecture beh of first_tb is

-- This is the component declaration 
  component first 
  port (
    SW:         in std_ulogic_vector(9 downto 0);
    LEDR:       out std_ulogic_vector(9 downto 0)
    );
  end component;

-- Signal declaration for the switches and the leds
  signal switch, ledr : std_ulogic_vector(9 downto 0); 

begin

-- Here the device under test is instantiated
  first_i0 : first
    port map (
      SW                  => switch,
      LEDR                => ledr);

-- This is the process where the switch is switched. Note that the process
-- always starts from the beginning. This process is not synthesizable because
-- of the wait statement. 
      
  schalter : process
  begin
    wait for 1 us; 
    switch <= "0000000001";
    wait for 3 us;
    switch <= "1000000000"; 
  end process schalter;

end; -- architecture
</code>