msvsli_start

Table of Contents

Master VLSI

Master VLSI

Master VLSI - From RTL to GDSII

Material

Course: https://github.com/fredowski/Course (see branch “tha”)

OpenROAD flow scripts: https://github.com/fredowski/OpenROAD-flow-scripts (see branch “vhdl”)

IHP PDK: https://github.com/IHP-GmbH/IHP-Open-PDK

SiliWizz: https://tinytapeout.com/siliwiz/introduction/

Andrew B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure, Springer, 2022

VLSI Physical Design - Slides , 2022

Onur Mutlu, Digital Design and Computer Architecture, ETH Zürich, 2026

Introduction and Overview

Youtube: Matt Venn - Inside the Cleanroom at IHP

OpenROAD Flow

Video: Youtube: "OpenROAD - Turning Designs into Optimized Silicon" - Matt Liberty (Latch-Up 2023)

Process Design Kit (PDK)

Timing Verification / Static Timing Analysis

Timing Analysis and Pipelining

Andrew Kahng - Chapter 8 Slides - Timing Closure

Partitioning / KL Algorithm

Andrew Kahng - Chapter 2 Slides - Partitioning

Placement

Andrew Kahng - Chapter 4 Slides - Placement

OpenROAD uses the RUDY Routing Congestion Estimation based on the following paper:

P. Spindler, F. M. Johannes, Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement, in Design, Automation and Test in Europe Conference 2007, April 2007. DOI: 10.1109/DATE.2007.364463.

Routing

Andrew Kahng - Chapter 5 Slides - Global Routing

Andrew Kahng - Chapter 7 Slides - Clock Tree Synthesis

Machine Learning in Chip Design

Felipe Sens Bonetto, Apply autoresearch to a RISC-V CPU design, github 2026

Youtube: Jeff Dean, Jeff Dean: AI will Reshape Chip Design, NeurIPS 2024

Chung-Kuan Cheng, Andrew B. Kahng, et al., "An Updated Assessment of Reinforcement Learning for Macro Placement", arxiv.org, March 2026