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--- msvsli_start [2026/04/27 13:35] – [Material] add ETH Zürich beckmanf
+++ msvsli_start [2026/06/01 15:44] (current) – [Process Development Kit (PDK)] beckmanf
@@ Line 32: / Line 32: @@
 [[https://raw.githubusercontent.com/fredowski/Course/tha/build/c04_lecture.pdf | Chapter 04 pdf]]
-==== Process Development Kit (PDK) ====
+==== Process Design Kit (PDK) ====
 [[https://raw.githubusercontent.com/fredowski/Course/tha/build/c05_lecture.pdf | Chapter 05 pdf]]
@@ Line 41: / Line 41: @@
 [[https://www.ifte.de/books/eda/chap8.pdf | Andrew Kahng - Chapter 8 Slides - Timing Closure]]
+==== Partitioning / KL Algorithm ====
+[[https://www.ifte.de/books/eda/chap2.pdf | Andrew Kahng - Chapter 2 Slides - Partitioning]]
+==== Placement ====
+[[https://www.ifte.de/books/eda/chap4.pdf | Andrew Kahng - Chapter 4 Slides - Placement]]
+OpenROAD uses the RUDY Routing Congestion Estimation based on the following paper:
+[[https://ieeexplore.ieee.org/document/4211973 | P. Spindler, F. M. Johannes, Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement, in Design, Automation and Test in Europe Conference 2007, April 2007. DOI: 10.1109/DATE.2007.364463.]]
+==== Routing ====
+[[https://www.ifte.de/books/eda/chap5.pdf | Andrew Kahng - Chapter 5 Slides - Global Routing]]
+[[https://www.ifte.de/books/eda/chap7.pdf | Andrew Kahng - Chapter 7 Slides - Clock Tree Synthesis]]
+==== Machine Learning in Chip Design ====
+[[https://github.com/FeSens/auto-arch-tournament/blob/main/docs/auto-arch-tournament-blog-post.md | Felipe Sens Bonetto, Apply autoresearch to a RISC-V CPU design, github 2026 ]]
+[[https://youtu.be/2A3tiAmaq_c?t=1480 | Youtube: Jeff Dean, Jeff Dean: AI will Reshape Chip Design, NeurIPS 2024 ]]
+[[https://arxiv.org/pdf/2302.11014 | Chung-Kuan Cheng, Andrew B. Kahng, et al., "An Updated Assessment of Reinforcement Learning for Macro Placement", arxiv.org, March 2026 ]]